Block Diagram

The following is a block diagram of the OSK5912:

A full description of the board can be found in the OSK5912 Hardware Specification on the OSK5912 CD-ROM. The main features of the board are:

• OMAP5912 processor (192MHz ARM, 192Mhz DSP)
• 32Mb Mobile DDR SDRAM
• 32Mb on-board Flash
• 10 Mbit Ethernet interface
• USB Host interface
• AIC23 stereo codec
• RS-232 serial port

The board is powered from a +5V DC input using the included AC power adapter. The OMAP5912 uses a 12MHz oscillator as a clock input with internal operating frequencies generated by on-chip PLLs. JP3 is typically the only jumper a user will modify. The Flash memory is physically connected to CS3. When JP3 is in the 2-3 position (default), the OMAP5912 boots in fast boot mode where CS3 is swapped with CS0 so the Flash starts at address 0. When the processor starts running, it will execute the code in Flash (U-Boot is stored in Flash at the factory).

If JP3 is in the 1-2 position, the OMAP5912 comes up in full boot mode with the internal ROM at address 0. The internal bootloader supports additional boot modes such as booting from the serial port. At any time, the state of the CS0-CS3 mapping can be changed by modifying the BM (bit 1) of the EMIFS_CONFIG register (address 0xFFFECC00).